Reed-Solomon decoding of data read from DVD or CD supports

ABSTRACT

An effective organization and transferring of data among the functional blocks of an integrated system of a read channel of data recorded on DVD-Rom, DVD-Ram, DVD-R or CD Rom for performing Reed-Solomon decoding including off-line heroic correction, or deinterleaving, Reed-Solomon decoding is provided. The integrated system includes an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM accessed through a 17-bit bus, a descrambling and EDC control block for DVD modes of operation, a descrambling block for CD codes of operations, a data output interface, and a timing control block. The system permits the de coding of the input data acquired through the input buffer at a rate of up to four-times the reference bit rate of DVD formatted data using a clock for accessing the embedded RAM having a frequency half that of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the decoding.

FIELD OF THE INVENTION

The present invention relates to a read-channel circuitry of data readfrom a mass memory support such as a DVD or a CD and more in particularto an integrated system for decoding according to the Reed-Solomonalgorithm data read from a mass memory support coded according tostandard DVD-ROM, DVD-R, DVD-RAM or CD-ROM protocols.

BACKGROUND

DVD and CD optical supports are more and more used for storing largequantities of data in PC's, digital audio and video playback systems andthe like. The storing and reading of data to and from these supportsimply the coding and decoding of data according to standard protocolsthat are defined at international level (e.g. ISO/IEC, CEI/IEC, etc.).

In write-read channel circuitry, reliability in terms of ability ofdetecting and correcting errors, especially during a phase of decodingof the coded data read from the support during a reading phase, andspeed are of paramount importance. Obvious cost-effectivenessconsiderations call for the highest level of integration of systemand/or subsystem circuitries in the minimum number of distinctintegrated circuits. Multifunctional Reed-Solomon decoders, capable ofhandling either DVD decoding and correction or CIRC decoding andcorrection for all the commonly used CD-modes should be advantageouslyintegrated in a single device including-an embedded RAM required for thedecoding and correction operations on a bitstream of input data asproduced by the data aquisition means of the read channel.

An architectural layout of such a multifunctional decoder ECC-IC isdepicted in FIG. 1.

The integrated decoder handles CD modes bitstreams of any format as wellas DVD-ROM, DVD-RAM and DVD-R mode bitstreams and advantageously shouldpossess speed capabilities of handling bitstreams equivalent to asignificantly large multiple of standard or base CD rates and ofstandard or base DVD rates.

With reference to the functional diagram of FIG. 1, the multifunctionalintegrated decoder ECC-IC, when operating in DVD mode, performshorizontal and vertical decoding of the input data stream and thedecoded data are then descrambled and EDC checked before sending them toan output interface circuitry. When operating in a CD mode, the data aredecoded and deinterleaved without performing any C3 decoding. Finally,when functioning in a BCA mode, the integrated decoder may perform aBurst Cutting Area decoding of the data stream.

The input data stream consists of the signals output by a dataaquisition IC as depicted in FIG. 2. The signals contain data,information about the data and address information.

byte_clk [1]

The byte_clk (byte clock) signal indicates that the data byte can beread. It is generated once per data byte for 1 system clock cycle.

erasure [1]

The erasure bit is set to 1 if the current data byte is not a valid 16/8modulation pattern (14/8 for CD)—if the pattern is valid, erasure is setto 0.

data [8]

The 8-bit data bus contains the demodulated data byte.

SID [4]

The 4-bit SID (sector ID) contains the 4 least significant bits of thelogical sector ID. This signal provides the sector address within eachblock.

id_error [1]

An id_error bit of 0 indicates that the SD was decoded with no errorsand no corrections. If the SID contained errors (no correction possible)or if a single error was corrected, the id_error bit is set to 1.

DVD/BCA frame_address[4:0] or CD S0/S1

In DVD modes the acquisition part keeps a memory of the syncs receivedand from this history extract the 5-bit frame address.

In BCA mode frame_address[3:0] depends from the sync found (SB_(BCA),RS_(BCA) 1, . . . , RS_(BCA)n, RS_(BCA) 13, RS_(BCA) 14, RS_(BCA) 15).

In CD mode the S0 and S1 signals are sent on frame_address[0] andframe_address[1] respectively.

CD nxfr [1] or DVD next_frame[1]

The DVD next_frame indicates that a new DVD frame is starting. The CDnxfr signal indicates that a new CD frame is starting. The BCAnext_frame indicates that a BCA Re-sync has been found.

The timing diagrams of the input data aquisition for the case ofoperation in DVD mode and in CD mode are shown in FIGS. 3 and 4,respectively.

ECC-IC has two kinds of output interface: one for CD-modes (serial) andone for DVD-modes (parallel). In particular, the CD output interface maybe a common I² S interface employing a format as depicted in FIG. 5, andthe subcode interface has as format as depicted in FIG. 6.

The Reed-Solomon decoder block depicted in FIG. 7, supports five mainmodes:

1) DVD Outer code (208, 192, 17) 8 errors or 16 erasures 2) DVD Innercode (182, 172, 11) 5 errors or 10 erasures 3) CD C1 code (32, 28, 5) 2errors 4) CD C2 code (28, 24, 5) 2 errors or 4 erasures 5) BCA code (52,48, 5) 2 errors or 4 erasures

The number of erasures that can be corrected is programmable, dependingon the mode, from 13 up to 16 for DVD Outer, from 7 up to 10 for DVDInner, from 1 up to 4 for CD C2. The Reed-Solomon block can beprogrammed to make a severe check for “miscorrections”: Thispreselection will cause a reduction of the decoding performance.

THE ERROR CORRECTION ALGORITHM

The complete algebraic decoding algorithm for the errors and theerasures is summarized in the following steps:

STEP 1. Calculation of the syndrome S(z), the erasure locator polynomialE(z) and the calculation of the modified syndrome T(z). If r(x) is thereceived code word$S_{j} = {\sum\limits_{i = 0}^{n - 1}\quad {r_{n - 1}\alpha^{ji}}}$

If α^(jk) is the position of a k-erasure and e is the number of erasures${E(z)} = {\prod\limits_{k = 1}^{e}\quad \left( {1 - {z\quad \alpha^{jk}}} \right)}$

If t is the maximum number of errors the code is able to correct

T(z)=S(z)E(z)mod(z ^(2t))

STEP 2. Perform the extended Euclidean Algorithm (modified version) tocalculate the error locator polynomial σ(z) and the error evaluatorpolynomial ω(z). Calculation of the new error locator polynomial Ψ(z)

Ψ(z)=σ(z)E(z)

STEP 3. Perform the Chien search to find the roots of the new errorlocator polynomial. The roots of this polynomial indicate the error anderasure positions in a received code word. Perform the Forney'salgorithm to find the error and erasure values.

STEP 4. Check the decoding process and correct the received code word.

The timing control block sets the control inputs of the Reed-Solomonblock and send start syndrome pulse (start_synd) with the first symbolof the code word.

The en_synd is acting as an enable for the data bus (data_in).

Every erasure should be flagged by erasure_pos. During the shifting ofthe code word, the Reed-Solomon calculates its syndrome and its erasurepolynomial.

Once the code word is completely shifted into the Reed-Solomon, thecontroller has to start the Key Equation Solver (start_kes).

The Reed-Solomon responds when error and location values are ready forthe controller (kesready).

The errors and error locations are stored in a Lifo and the controllercan read them with read_pos and read_error signals.

The Reed Solomon processing consists of three main tasks:

a) syndrome and erasure polynomial calculation (invoked by start_synd)

b) key equation solving and error calculation (invoked by start_kes)

c) Chien & Forney (generating the ending signal kes_ready)

as depicted in the block diagram of FIG. 8.

In DVD Outer decoding, the erasure polynomial is equal for each column,because it is calculated using the incorrectable flag coming from theInner decoding. For this reason it is calculated only once for each Eccblock of data at the beginning of the vertical decoding process; theresulting polynomial is stored depending on the store_eras_poly signal.This is depicted by way of a block diagram in FIG. 9.

During the DVD decoding process (Inner-Outer-Inner-Outer- . . . ) thesignal sel_eras_poly send to Key Equation Solver the current erasurepolynomial (Inner) or the previous stored erasure polynomial (Outer).

SUMMARY OF THE INVENTION

To overcome the intrinsic low speed of embedded DRAMs it has been foundthat a considerable increase of the required processing speedcapabilities in a fully integrated decoder (ECC-IC) may be obtained byorganizing the data flow within the integrated decoder and the embeddedRAM in a way as to reduce the number of accesses to the embedded RAMneeded to perfom the decoding at the required speed while using theReed-Solomon decoding block at twice the maximum clock frequency allowedby the embedded RAM (25 MHz).

Accordingly, in DVD decoding, the syndrome engine is made capable toprocess two code words at the same time, by storing the finalpolynomials into distinct registers: two for storing vertical syndromesand one for storing horizontal syndromes, thus implementing a kind ofparallel processing in the decoding phase.

Accordingly, in CD decoding, a new addressing scheme has been found toperform very high speed M2 deinterleaving, minimizing the number ofaccesses to the embedded DRAM required to perform the deinterleaving ofdata.

The embedded DRAM is organized in distinct banks, each divided into anumber of pages of certain capacity of words, functioning in asynchronous page mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an architectural layout of the multifunctional decoder ECC-ICof the invention;

FIG. 2 shows the input data coming from a data acquisition IC;

FIGS. 3 and 4 show the timing diagram of the input data acquisition forthe case of operation in DVD mode and in CD mode, respectively;

FIGS. 5 and 6 illustrate the output serial I²S data interface for CDmode and the output serial subcode interface for CD mode, respectively;

FIG. 7 represents the Reed-Solomon Decoder block;

FIG. 8 schematically shows the processing performed by the Reed-SolomonDecoder;

FIG. 9 schematically illustrates the processing of erasure flags duringhorizontal and vertical DVD decoding;

FIG. 10 shows the parallel processing of partial syndrome values;

FIG. 11 shows the timing diagram of the embedded DRAM working in asynchronous page mode, for a word access in first cycle;

FIG. 12 shows the functional blocks of the ECC-IC device that areinvolved with the data flow in a DVD mode of operation;

FIG. 13 illustrates schematically the different phases of processing(DVD mode);

FIG. 14 shows the particular mapping adopted for the embedded DRAM forone ECC-block of data;

FIG. 15 illustrates the output processing;

FIG. 16 illustrates the processing referred to a complete elaborationtime frame, divided in four steps;

FIG. 17 shows the functional blocks of the ECC-IC device that areinvolved with the data-flow for the case of a CD mode of operation;

FIG. 18 illustrates the first step of the deinterleaving(M1-deinterleaving) of input data;

FIG. 19 illustrates the particular mapping inside a page of the embeddedDRAM (M2-deinterleaving);

FIG. 20 shows deinterleaved frames read from the DRAM;

Table 1 illustrates the particular mapping of the two banks of DRAM(M2-deinterleaving) refering to the input frame numbers.

FIG. 21 depicts the enable signal according to the different framenumbers;

FIG. 22 shows the particular mapping inside a page of the embedded DRAM(M3-deinterleaving);

FIG. 23 illustrates schematically the different phases of processing (CDmode);

FIG. 24 illustrates how one block of 12 words is read from memory foreach input frame;

FIG. 25 shows the functional blocks of the ECC-IC device that areinvolved with the data flow during operation in BCA mode;

FIG. 26 illustrates the mapping of the embedded DRAM (BCA mode);

FIG. 27 illustrates schematically the different phases of processing(BCA mode)

FIG. 28 depicts the descrambling architecture for DVD mode of operation;

FIG. 29 depicts the descrambling architecture for CD mode of operation;

FIG. 30 shows the functional block diagram of the EDC checker;

FIG. 31 depicts the way the new CRC value is produced by shifting theold value and xoring the result with the updating value.

DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

An integrated multifunctional Reed-Solomon decoder according to thegeneral characteristics already described above and embodying thefeatures of the invention, implementing the method of the invention oforganising and transferring data among the functional blocks of theintegrated decoder will now be described with reference to the drawings.

With reference to the diagram of FIG. 10, the synd2 value (rs_reg[2]),if set, selects for each byte_clk a different syndrome register (SK1,SK2) to store the polynomials related to the two different columns. Thesel_synd_poly signal chooses which one of the stored syndrome values isto be sent to Key Equation Solver (KES).

Timing Control Block

According to the sample embodiment taken into consideration, thefollowing assumptions were made:

The system clock speed is 50 MHz.

The symbols coming from the data acquisition block are stored into aninput memory working with the system 50 MHz clock.

The embedded DRAM works in a synchronous page mode with a 25 MHz clock.

DVD×4 and CD×32 are taken as target speed capabilities for the relativemodes (two steps of decoding for DVD modes and complete CIRC decodingfor CD modes).

The byte clock coming from the data acquisition device is alwaysavailable.

At the output of ECC-IC only complete Ecc blocks of data will be output.

The characteristics of the DRAM embedded in the ECC-IC chip were thefollowing:

1-Transistor Planar memory cell.

Planar Memory cell area: 11.2 mm2.

Organized in three banks of 16K words of 17 bits, split into 512 rows of32 words of 17 bits.

Byte-Write capability available, i.e. write operation can be applied toany of the two bytes. Read operation is always done on 17 bits.

512-cycle refresh distributed across 1 ms.

No Redundancy

Latched Output Data.

Bidirectional data bus.

On-chip voltage generators

Separate I/O data buses with write-through enable pin.

During page modes, row addresses are latched for the duration of wholerow access, i.e until precharge is performed, while column addresses arelatched only during the actual column access.

Row is accessed first, then words in that row (or page) at a rate of oneword per cycle. An extra cycle is required to go back to prechargebefore accessing a new row.

There is no specific Refresh cycle. Any Read or Write operation is alsoa refresh cycle.

The timing diagram of the embedded DRAM working in a synchronous pagemode, for a word access in first cycle, is shown in FIG. 11.

The Timing Control block is responsible of scheduling data transferamong the following functional blocks that compose the ECC-IC of FIG. 1:

Input interface

Input memory

Reed Solomon decoder

DRAM (embedded in the IC)

Descrambling and EDC checker (for DVD mode of operation only)

Descrambling (for CD modes of operation only)

Output interface

DVD Mode of Operation

Processing of data starts each time a couple of rows have been received.

The decoder ECC-IC performs the following operations:

horizontal correction of 2 rows, Ecc-block(#n).

vertical correction of 2 columns, Ecc-block(#n−1) (this operation startsonly when the horizontal correction of this Ecc-block has beencompleted).

output of 2 rows, Ecc-block(#n−1) or Ecc-block(#n−2) (this operationstarts when the vertical correction of the Ecc-block has beencompleted).

In order to support a sequential reading, the ECC-IC must complete theabove processing before a new couple of rows is received.

The minimum time frame when operating in a DVD×4 mode is 56.875 usec(2×182/6.4 MHz).

FIG. 12 shows the functional blocks of the ECC-IC device that areinvolved by the data flow in a DVD mode of operation.

Normal Mode

Data and erasure flag coming from the data acquisition IC are sampledinto Input interface and stored frame after frame into one of the twoInput RAMs.

Each time 4 frames (equivalent to two rows) have been received, theinput is switched on the second RAM; the previous rows are read fromthis memory and sent both to the Reed-Solomon decoding block, tocalculate Inner syndromes and corresponding erasure polynomial, and tothe embedded DRAM, where two complete ECC blocks of data are stored.

ECC-IC performs at the same time the Inner decoding of Ecc block #n andthe Vertical decoding of Ecc block #(n−1).

Flags coming from Inner decoding are stored into DRAM to be used laterin Outer decoding: for Row_(n), the erasure flag is stored into the(Row_(n), Col₁₈₂) word. Horizontal corrections are effected (up to 5errors or 10 erasures) within the DRAM.

While storing rows into one Ecc block in the DRAM, columns of theprevious Ecc block are being decoded. Each time a word is read fromDRAM, bytes of two different columns are retrieved, therefore thesyndrome engine is able to calculate syndromes of both columns at thesame time.

Vertical corrections are effected (up to 8 errors or 16 erasures) withinthe DRAM.

When an Ecc block is completely decoded vertically, the outputprocessing begins: data are read by rows from DRAM and sent to thedescrambler block, and successively to the EDC checking block andfinally to the output interface block.

Each time EDC fails, a bit is set into a register (16 bits), containingthe results of each sector. At the first fail an interrupt is generatedtowards the μP.

Cycles are inserted to guarantee complete refreshing of the embeddedDRAM.

The different phases of processing are schematized in FIG. 13.

Each Elab frame starts only when two complete rows have been receivedand are ready to be horizontally decoded and stored into DRAM. For thisreason the byte clock should never disappear, in order to avoidarresting the internal processing.

In the time frame two new rows are received, two rows and two columnsare decoded. Therefore, the Elab time frame must be shorter than twicethe shortest Input data time frame (DVD×4)=2*(28.43 usec).

In view of this length of each Elab frame, the decoding core will bealways waiting for the rows_ready signal. If for any reason (as forexample an unlocked DPLL) the Input data frame will be shorter than Elabframe the latest stored row will be overwritten in the Input RAM by datacoming from the data acquisition IC.

With a DRAM functionning in synchronous page mode, each time a new pagehas to be accessed, one extra cycle is needed to perform thepre-charging of the page. In one page of DRAM, 16 bytes per row and 12bytes per column are stored: 1 row=12 pages, 1 column=18 pages. To store2 Ecc blocks 432 pages are necessary. 32 rows are refreshed during eachElab frame.

At the end of each Elab frame, the core waits for the next two rows todecode, while refreshing the DRAM. As soon as a new couple of rows isreceived ready to be decoded, the process restarts.

Heroic Correction

If for any reason the output data are still affected by errors, the μPmay decide to initiate a more effective decoding of a specific Ecc blockof data.

The μP can decide how many iterations of decoding should be done(Inner-Outer-Inner-Outer- . . . -Inner-Outer); the maximum number ofECC-blocks is written in a ECC_block register, the number of iterationis written into a nb_iter register and the process is started settinganother bit in the same register (HC).

Data coming from the data acquisition IC are horizontally and verticallycorrected as in normal mode. The flags generated from the verticaldecoding are stored into DRAM to be used as erasure flags in thehorizontal decoding step of the selected Ecc-block.

At the end of the vertical decoding the ECC-block number is comparedwith the value written in the Ecc_block register. If the ECC-blocknumber matches, the input is disabled and the next step of decodingtakes place on this ECC-block: for Col_(n) the erasure flag is storedinto the (Row₂₀₈, Col_(n)) word.

Data are read towards the DESCRAMBLING, EDC AND OUTPUT INTERFACE blocksand, at the same time, horizontal syndromes are calculated andcorrections applied within the DRAM.

At the end of the Ecc block, if any of EDC check bit is set and if themaximum number of iterations is not reached the process go ahead withanother vertical decoding step and so on.

When all the EDC checks are right or when the maximum number ofiterations has been reached, an interrupt is generated and theprocessing is stopped.

The algorithm may be expressed as follows:

STEP1: read Ecc blocks from disk. Normal decoding of data with check,after vertical step, of the Ecc-block number. No output of data duringthis step. This phase is repeated until the right Ecc-block number willbe found. When this happens, the input of following data will bedisabled.

STEP2: Output data+EDC check+Inner correction (use flag coming fromouter decoding as erasure flag).

if (EDC is OK) OR (maximum number of iterations is reached)

STOP

else

vertical correction

repeat this step

Long Mode

If a specific bit is set into a dedicated register (longm), the ECC-ICmay work in long mode: the decoding process is still active but no datacorrection is effected and all bytes received from acquisition (userbytes+parity bytes) are sent to the output interface.

Input RAM

Two static Ram, each one 2 rows wide (2×182×9 bits), are employed.

While data are stored into one RAM frame after frame, the previous tworows are read from the other RAM. Only when two rows are completelybuilt, the transfer to Reed-Solomon decoder and to the embedded DRAMbegins.

For each location 1 byte and its erasure flag coming from thedemodulation process are stored.

Embedded DRAM

3 banks of 16K×17 bits of DRAM memory are employed. Each bank is splitinto 512 rows of 32 words of 17 bits.

In DVD mode the three banks are addressed as a single memory; each ECCblock is stored according to the following mapping: in each page(3×32×17 bits) 16 bytes of one row and 12 bytes of one column arestored.

To store or to retrieve a complete row, 12 pages must be addressed, toread a complete column, 18 pages must be addressed.

In this mode, the 17th bit of each location becomes meaningless.

An extra-row (Row₂₀₈) and an extra-column (Col₁₈₂) are needed to storeerasure flags coming from Inner and Outer decoding.

According to an important aspect of this invention, an effective mappingbecomes intrumental in reducing as much as possible the number ofaccesses to the DRAM.

By operating in a synchronous page mode, a cycle is lost at each changeof page, because a precharge cycle is normally needed.

By contrast, if when changing page the bank of DRAM is also changed, noextra cycle is needed. In practice, in writing a row, the page and alsothe DRAM bank are changed: every 16 bytes (bank0-bank1-bank2-bank0- . .. and so on).

Therefore, in retrieving a column from the embedded DRAM during thedecoding, it is always true that a page change occurs only when changingbank (from bank2 to bank0), thus there are no extra cycles.

Extra cycles are needed only during horizontal and vertical correction,because in those operations, it may happen to be changing page whileremaining in the same bank of the embedded DRAM.

Of course, also during refresh there occurs an extra cycle, because allthe banks are refreshed at the same time (dummy read).

The particular mapping of the embedded DRAM for one Ecc_block of data isdepicted in FIG. 14.

To store one Ecc_block 216 pages are needed. Refresh is effected onlyfor 432 pages of the DRAM because two Ecc_blocks of data are needed forthe processing.

Output Interface—DVD Modes

Decoded sectors are read from DRAM row after row, descrambled and EDCchecked if needed. The pages are read from memory (max 16 bytes, min 6bytes) and stored into the output buffer (24 bytes).

When SREQI is asserted by an ATAPI-IC, data available in this buffer areread and sent to the output.

During the processing of input data the Timing Control samples thestatus bit of the output buffer to be ready to store another page ofdecoded data read from the DRAM as soon as enough data are sent to theATAPI-IC.

Until the Elab frame is finished, 2 rows as maximum can be trasmitted tothe output buffer. Instead at the end of internal processing and duringrefresh cycles, as many data as required by the ATAPI-IC are sent to theoutput buffer. For this reason decoded ECC blocks are sent to theATAPI-IC always at the maximum speed allowed by SREQI signal.

The output process is depicted in FIG. 15.

Parallel Vertical Syndromes Computation

During vertical decoding, data are retrieved from DRAM word after word;in each word a byte belonging to one column and another belonging to thenext one are identified. The Reed-Solomon decoder decodes at the sametime data of the input rows and data of these columns.

The processing is depicted in FIG. 16. The Elab frame (computation timeframe) may be divided in four steps:

Step1.

Horizontal syndrome computation (row#m, Eccb#n)

Horizontal erasure polynomial computation (row#m, Eccb#n)

Vertical syndrome decoding (col#p, Eccb#n−1)

Step2.

Horizontal syndrome computation (row#m+1, Eccb#n)

Horizontal erasure polynomial computation (row#m+1, Eccb#n)

Horizontal syndrome decoding (row#m, Eccb#n)

Step3.

Vertical syndromes computation (col#p+2,p+3, Eccb#n−1) (to be continued)

Vertical syndrome decoding (col#p+1, Eccb#n−1)

Step4.

Vertical syndromes computation (col#p+2, p+3, Eccb#n−1)

Horizontal syndrome decoding (row#m+1, Eccb#n)

During step3 and step4, the first column of the Eccb#n−1 to be read fromDRAM is Col₁₈₂, containing the erasure flags from horizontal decodingfrom which the vertical erasure polynomial is updated and stored too.

CD Modes of Operation

The functional circuit blocks of the ECC-IC involved into CD data floware shown in FIG. 17.

In CD-modes the 3 banks of the embedded DRAM are used as three differentmemories: M2-deinterleaving is carried out in two of the banks, whileM3-deinterleaving is performed in the third bank.

Data received from the data acquisition IC is stored into Input RAM(user data) or sent to output interface (subcode data and sync). Foreach F3 frame 32 bytes of user data are stored, each one with itserasure flag.

The first step of the deinterleaving (M1-deinteleaving) takes place intothe Input RAM according to the sheme of FIG. 18.

Data are read from this memory deinterleaved, sent to Reed-Solomondecoder and stored into the correction FIFO. In this step theReed-Solomon core calculates the C1 syndrome of the input frame.

Meanwhile, the previous frame stored into the FIFO is corrected on thefly and stored into the two banks (DRAM1, DRAM2) of the DRAM, organizedin 512 pages of 32*17 bits each, according to a mapping as schematizedin FIG. 19: the 28 bytes frames are stored in one DRAM page togetherwith its C1 decoding flag. In a page of one bank of DRAM two 28bytes-frame can be stored. The M2-deinterleaving takes place in thesetwo banks of DRAM.

According to an important aspect of this invenction, an effectiveaddressing of the incoming frames together with the mapping of FIG. 19becomes instrumental in reducing as much as possible the number ofaccesses of the DRAM, allowing to perform a very high speedM2-deinterleaving. 112 frame need to be stored in the two banks,requiring 28 pages of DRAM1 and DRAM2: therefore only these pages needto be refreshed.

Tab. 1 in FIG. 20B shows the content of the two banks (DRAM1, DRAM2)after 112 frames have been received. Depending on the circular approachchosen, frame#113 and frame #121 will be stored in page#0 of DRAM1 andso on.

Functioning in a synchronous page mode, the embedded DRAM needs a cyclefor precharge each time a new page is addressed.

Frames coming from the correction FIFO are corrected on the fly andstored in DRAM1 or into DRAM2: 32 corrected bytes are read from the FIFObut only 28 bytes are stored into DRAM, because the parity bytes can bediscarded.

The operations performed when a frame is written into the right DRAMbank are:

select the right bank and the right page

write 14 words (17 bits) into the memory

To write a complete frame we need (1+14)cycles.

Data for C2 syndrome calculation (28 bytes+flags) are read from M2memory: the new mapping of the data allows to reduce the number ofaccesses of the DRAM needed to retrieve both deinterleaved data andcorrespondent flags.

FIG. 20A shows that to retrieve a complete deinterleaved frame(1+2)*8=24 DRAM cycles are needed. In fact, to read a deinterleavedframe, 8 pages are addressed and 32 bytes retrieved: only 28 bytes aresignificant.

Firstly, the page where to start from must be decided, according to${firstPAGE} = {{4\left\lfloor \frac{frame}{16} \right\rfloor {{mod}(28)}} + {{frame}\quad {{mod}(4)}}}$

where “frame” stands for the frame number.

From each selected page 4 bytes in 2 cycles are read, two from DRAM1,two from DRAM2: for example, if page#0 is selected, in the first cycle abyte from frame#1 (DRAM1) and one from frame #5 (DRAM2) are read, in thesecond cycle a byte from frame #3 (DRAM1) and one from frame #9 (DRAM2)are read.

Every time 1 bytes from a page are retrieved, the page number isincremented according to

nextPAGE=(PAGE+4) mod(28)

At this point, from the 32 bytes read, the 28 significant bytes arechosen: they are always consecutive but the first significant bytechange position each 4 frames, still remaining in the first selectedpage.${firstBYTE} = \left\lfloor \frac{{frame}\quad {{mod}(16)}}{4} \right\rfloor$

The enable signal is shown in FIG. 21, according to the different framenumbers. The waveform of this signal repeats itself every 16 frames.

M2-deinterleaved data are read from DRAM, sent to the Reed-Solomondecoder and stored into the correction Fifo again. In this step theReed-Solomon core calculates the C2 syndrome.

The previous frame stored into the Fifo is corrected “on the fly” andstored into the M3 memory bank. Deinterleaved data are read from the M3bank and sent to the output interface.

The third step of deinterleaving is done into the third bank (M3) ofDRAM, organized in 512 pages of 32*17 bits each, by using only two pagesfor the process.

To perform this third step of deinterleaving four frames coming from C2decoding are stored, each byte coming with its flag of correct/incorrectdecoding.

First of all, two bytes are packed in one word ready to be written intoM3, therefore for each couple of bytes only 1 flag in 17th position iswritten.

The mapping of the M3 DRAM memory is shown in FIG. 22.

The operations performed when a frame is written into the M3 memory are:

select the right page

write 12 words (17 bits) into the memory

To write a complete frame we need (1+12) cycles

The operations performed when a frame is read from the M3 memory are:

select the right page

read 12 words (17 bits) from the memory, two words from frame (N) thentwo words from frame (N−2)

To read a complete frame we need (1+12) cycles.

The Elab_frame is illustrated in FIG. 23.

The elaboration time frame must be shorter than the shortest Input timeframe (for CD×32 rate it is of 4.25 usec).

The Elab frame start only if there is a new F2-frame to be decoded.

The C1-syndromes update time depends from the speed of the disk, becausethe Input memory is shared between the input process and the CIRCdecoding.

The refresh of twenty eight pages is done at the same time on the threebanks of the DRAM.

At the end of an Elab frame refresh cycles are inserted until a newF2-frame is ready for decoding.

Output of Data in CD Modes

Data are read from the third bank of the DRAM (M3), frame after frame,and are sent to the CD-descrambler (if enabled) and to output interface.

One block of 12 words is read from memory for each input frame asillustrated in FIG. 24. Each byte read from DRAM is sent to the outputbuffer.

BCA Mode Operation

BCA is an area for recording information after finishing discmanufacturing process. The data in the BCA-Code consists of aBCA-preamble field, a BCA-Data field and a BCA-Postamble field. Thelength of BCA-Data field is (16n−4) bytes, with 1≦n≦12. These bytes areencoded with a Reed-Solomon code (52,48,5) and protected by a 32 bitsCRC.

FIG. 25 shows the functional blocks of the ECC-IC device that areinvolved by the data flow in a BCA mode of operation.

A SRAM (364×9 bits) is used for storing the incoming data. The syncinformation is carried by frame_addr[4:0].

Data are stored into Input RAM to reconstruct the complete block. Whenthe last sync (RS_(BCA15)) or the postamble pattern is received, thedecoding process starts.

Bytes are sent to the embedded DRAM and to the Reed-Solomon decoder tocalculate the syndromes of the four code words. During this transfer,zeroes are inserted to fit the code word length (if required). All thebytes (information+parity bytes=4*(48+4)bytes) are stored into DRAM,following the same addressing scheme as in DVD-modes: code word 0 isequivalent to Row0, code word 1 to Row1, code word 2 to Row2, code word3 to Row3. The mapping is illustrated in FIG. 26. Only 4 pages of DRAMneed to be refreshed.

Corrections are applied into the DRAM.

Data are read towards the EDC checker to test the result of thedecoding. The EDC flag is stored into an edc_register[0].

The end of processing is signalled to μP by interrupt. The μP will takecare of transferring data to the ATAPI buffer.

The Elab frame in BCA modes is illustrated in FIG. 27.

Acquisition and Timing Control—BCA Heroic-mode

If sync detection problems are experienced in the acquisition of data,the μP may decide to do the demodulation of BCA by firmware. Setting theHC bit in μP interface, data received from the data acquisition IC aresimply stored into the Input RAM. When the last byte is received, the μPbegins to read all the blocks from this memory. After carring outdemodulation and formatting of the data blocks, data are written back toInput RAM and the decoding process starts (as in normal BCA mode) whenthe Start bit in the μP interface is set by the μP.

DVD Descrambler

Data are descrambled just before reaching the EDC checker and Outputinterface. Bytes coming from the embedded DRAM after Reed-Solomondecoding are descrambled “on the fly” and then passed to the EDCchecker.

The basic descrambling operation is to forward one byte unchanged if itdoes not belong to the main data area, or to perform another XORoperation with the right scrambling value to retrieve the original data.The scramble value must be generate internally.

Each already error-corrected and deinterleaved data sector is treatedseparately (during descrambling), sequentially byte after byte (as partof an entire Ecc_block of data).

The overall architecture of the Descrambler for DVD mode is depicted inFIG. 28.

The main input is the sequential stream of data bytes. The row andcolumn indexes of the current input data byte are needed for algorithmcontrol. From such information principally the Sector_start (first byteof a new data sector) and the Block_start (first byte of a new Eccblock) must be retrieved.

The Desclamber is provided with the 50 MHz master clock and with adata_enable signal indicating that an input data has to be processed.

The main output is a stream of descrambled bytes, accompanied by controlsignals necessary for the EDC checker and output interface.

The Descrambler processes only DVD-data, depending on the format of theinput data. In the other modes of operation, the data bytes are simplyconveyed to the output.

CD Descrambler

Data (not audio) coming from CIRC decoding must be descrambled beforegoing to C3 decoding. This operation may be done inside ECC-IC or in anATAPI-IC. A bit written in a register (en_des) enables/disables thisfunction.

The incoming byte are xored with a scramble value generated by a FSR, asshown in the functional block diagram of FIG. 29.

The 15-bit register is of the parallel-block synchronized type and fedback according to the polynomial x¹⁵+x+1.

After the Sync of the sector (0x00, 0xFF ten times, 0x00) has beenfound, the register is preset with the value 0x0001, where 1 is theleast significant bit. A symbol counter will count 2340 bytes to bedescrambled.

Each time a Sync pattern is detected a preset is generated (the Syncwindow is always active) and the counter reset to 2340 (Short Sectors).

Each time the counter reaches zero, a preset signal is generated anyway,even if no Sync pattern is found. The counter is reset to 2340 (LongSector).

Each time a new byte is read, the FSR value St[15:0] is updated asfollows:

S_(t+1)[15]=S_(t)[8]xorS_(t)[7]

S_(t+1)[14]=S_(t)[7]xorS_(t)[6]

S_(t+1)[13]=S_(t)[6]xorS_(t)[5]

S_(t+1)[12]=S_(t)[5]xorS_(t)[4]

S_(t+1)[11]=S_(t)[4]xorS_(t)[3]

S_(t+1)[10]=S_(t)[3]xorS_(t)[2]

S_(t+1)[9]=S_(t)[2]xorS_(t)[1]

S_(t+1)[8]=S_(t)[1]xorS_(t)[0]

S_(t+1)[7:0]=S_(t)[15:8]

EDC Checker

The EDC is a CRC check which, in DVD-mode, is applied to the sectorsafter the descrambling has been performed. In BCA mode the EDC check iseffected to test the result of decoding.

BCA Mode

A decoded BCA block consists of 16×n bytes with 1≦n≦12. The last fourbytes are parity bytes, obtained dividing the information bits by thegenerator polynomial:

g(x)=x ³² +x ³¹ +x ⁴+1

At the beginning of each block a start signal resets the EDC value tozero. With each enable signal, data is read from the embedded DRAM tothe EDC.

The current value of EDC is updated each time a new byte is received.

After 192 bytes the check is stopped and a result flag is set to zero ifthe check was satisfactory. Otherwise this flag is set to 1. The EDCdoesn't change the data in any case.

The result flag of the block is stored into a register edc_reg[0], andan interrupt is generated towards the μP to signal the end of BCAprocessing.

The μP will take care to read the decoded bytes from internal DRAM to anATAPI buffer.

DVD Mode

Each sector consists of 12 rows*172 bytes. The EDC checker gives acorrect check if the error-correction has performed well. Of course,this check has no 100% safety, but a high probability that incorrectdata be recognized.

At the beginning of each sector, the start signal resets the EDC valueto zero. With each enable signal data is shifted from the DVDDescrambler to the EDC checker.

The current value of EDC is updated each time a new byte is received.

After 2064 bytes the check is stopped and the result flag is set to zeroif the check was satisfactory. Otherwise this flag is set to 1.

All the result flags of the sectors inside an Ecc_block of data arestored into a register edc_reg[15:0]; when the first EDC failure occurs,an interrupt is generated towards the μP; the content of this registerwill be reset when the first byte of the next Ecc_block will be output.

A functional block diagram of the EDC Checker is shown in FIG. 30.

Four bytes are attached to 2060 bytes in a data sector. Let's supposethat the MSB of the first byte of the sector is b16511 and the LSB ofthe last byte of EDC is b0.

The generator polynomial of the code is

g(x)=x ³² +x ³¹ +x ⁴+1

and the information polynomial is${I(x)} = {\sum\limits_{i = 16511}^{32}\quad {b_{i}x^{i}}}$

The implemented algorithm works directly on bytes. This allows to reducethe frequency of the clock needed in this processing.

An internal ROM storing 8 words of 32 bits is used to update the CRCvalue each time a new byte is received. The stored values are obtainedas remainder of the division$W_{i} = {R\left( \frac{x^{32 + i}}{g(x)} \right)}$

calculated in GF(2).

At the beginning of the sector the value of CRC is initialized to0x0000. The input byte is xored with the most significant byte of thecurrent CRC value: each “1” in the resulting byte enables one storedvalue; all the enabled bytes are xored to give an updating value. Thenew CRC value is obtained shifting the old one and xoring the resultwith the updating value. This processing is illustrated in the diagramof FIG. 31.

What is claimed is:
 1. A method of organizing and transferring data among functional blocks of an integrated system of a read channel for data recorded on DVD-Rom, DVD-Ram, and DVD-R for performing Reed Solomon decoding including off-line heroic correction, the integrated system including an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM accessed through a 17-bit bus, a descrambling and EDC control block for DVD modes of operation, a data output interface and a timing control block, wherein the decoding of input data acquired through the input buffer is performed at a rate of up to four-times a reference bit rate of DVD formatted data using a clock for accessing the embedded RAM having a frequency which is half that of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the decoding, the method comprising the steps of: a) organizing DVD mode input data in two blocks or rows of 182 bytes each; b) storing each block or row in 12 pages of distinct banks in which the embedded RAM is divided, functioning in a synchronous page mode, each bank being split into 512 pages of 32 words of 17 bits, by organizing bytes into words of 16 bits, sequentially readable therefrom without waiting for any precharge cycle; c) simultaneously decoding two input blocks or rows in the Reed-Solomon decoder, while correcting errors and storing decoding flags in the embedded RAM; d) refreshing the embedded RAM while the decoding of two blocks is in progress; and e) decoding two columns of 208 bytes each of the stored blocks or rows by reading columns word by word from the embedded RAM and performing parallel Reed-Solomon decoding on two columns at a time in the Reed-Solomon decoder, while correcting errors and storing decoding flags in the embedded RAM.
 2. A method of organizing and transferring data among functional blocks of an integrated system of a read channel for data recorded on a CD Rom for performing deinterleaving, decoding and correction, the integrated system including an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM accessed through a 17-bit bus, a descrambler, a data output interface and a timing control block, wherein the processing of the input data acquired through the input buffer is performed at a rate of up to 32 times a reference bit rate of CD formatted data using a clock for accessing the embedded RAM having a frequency which is half that of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the processing, the method comprising the steps of: a) sorting CD mode frames of input data including erasure flags in the input buffer and conveying subcode and sync data to the output interface; b) performing a first step of deinterleaving in the input buffer while reading frames of input data therefrom, inputting the frames to the Reed-Solomon decoder that calculates a C1 syndrome and storing the data frames in a correction fifo buffer while correcting errors on the fly of a previously stored frame and storing it in two banks of the embedded RAM; c) performing a second step of deinterleaving in the two banks of three distinct banks in which the embedded RAM is divided, functioning in a synchronous page mode, each bank being split into 512 pages of 32 words of 17 bits, by organizing bytes and C1-decoding flags into words of 17 bits, by storing data in 28 pages with a new addressing scheme, subject to refreshing, each page containing two of the frames, by reading frames of deinterleaving data and flags from the two banks, inputting the frames to the Reed-Solomon decoder that calculates a C2 syndrome and storing the data frames in a correction fifo buffer while correcting errors on the fly of a previously stored frame and storing it in a third bank of the embedded RAM; d) performing a third and final step of deinterleaving in the third one of the three distinct banks in which the embedded RAM is divided, using two pages for the process, including reading four frames of deinterleaved data from the two banks, each byte with its own flag of correct/incorrect decoding, and packing two bytes in one word to be written in the third bank of the embedded RAM; e) refreshing 28 pages of each of the three banks of embedded RAM simultaneously while a processing of one frame is in progress; and f) reading frames from the third bank of the embedded RAM and inputting them to the descrambler toward the output interface.
 3. A method of organizing and transferring data among functional blocks of an integrated system of a read channel for data recorded on at least one of DVD-Rom, DVD-Ram, and DVD-R for performing Reed Solomon decoding including off-line heroic correction, the integrated system including an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM divided into banks, a descrambling and error data correction control block for DVD modes of operation, a data output interface and a timing control block, wherein the decoding of input data acquired through the input buffer is performed at a higher rate than a reference bit rate of DVD formatted data using a clock for accessing the embedded RAM having a frequency which is a fraction of the frequency of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the decoding, the method comprising the steps of: a) organizing DVD mode input data in blocks; b) storing each block in a plurality of pages of the banks in which the embedded RAM is divided, for functioning in a synchronous page mode, each bank being split so into the plurality of pages of words of bits, by organizing bytes into words of bits, sequentially readable therefrom without waiting for any precharge cycle; c) decoding two input blocks in the Reed-Solomon decoder, while correcting errors and storing decoding flags in the embedded RAM; d) refreshing the embedded RAM while the decoding of two blocks is in progress; and e) decoding two columns of bytes each of the stored blocks by reading columns word by word from the embedded RAM and performing parallel Reed-Solomon decoding on two columns at a time in the Reed-Solomon decoder, while correcting errors and storing decoding flags in the embedded RAM.
 4. A method of organizing and transferring data among functional blocks of an integrated system of a read channel for data recorded on a CD Rom for performing deinterleaving, decoding and correction, the integrated system including an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM divided into banks, a descrambler, a data output interface and a timing control block, wherein the processing of the input data acquired through the input buffer is performed at a higher rate than a reference bit rate of CD formatted data using a clock for accessing the embedded RAM having a frequency which is a fraction of the frequency of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the processing, the method comprising the steps of: a) sorting CD mode frames of input data including erasure flags in the input buffer and conveying subcode and sync data to the output interface; b) performing a first step of deinterleaving in the input buffer while reading frames of input data therefrom, inputting the frames to the Reed-Solomon decoder that calculates a C1 syndrome and storing the data frames in a correction fifo buffer while correcting errors on the fly of a previously stored frame and storing it in two banks of the embedded RAM; c) performing a second step.of deinterleaving in the two banks of the embedded RAM, while functioning in a synchronous page mode, each bank being split into a plurality pages of words of bits, by organizing bytes and C1-decoding flags into words of bits, by storing data in pages with a new addressing scheme, subject to refreshing, each page containing two of the frames, by reading frames of deinterleaving data and flags from the two banks, inputting the frames to the Reed-Solomon decoder that calculates a C2 syndrome and storing the data frames in a correction fifo buffer while correcting errors on the fly of a previously stored frame and storing it in a third bank of the embedded RAM; d) performing a third step of deinterleaving in the third bank of the embedded RAM, using two pages for the process, including reading four frames of deinterleaved data from the two banks, each byte with its own flag of correct/incorrect decoding, and packing two bytes in one word to be written in the third bank of the embedded RAM; e) refreshing pages of each of the three banks of embedded RAM simultaneously while a processing of one frame is in progress; and f) reading frames from the third bank of the embedded RAM and inputting them through the descrambler to the output interface. 